Advanced lithographic processes, such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), are currently used in ultra-high density integrated circuits to provide an electrical interconnection system which includes multiple arrays of parallel mandrel and non-mandrel metal lines disposed in several levels of dielectric layers. The dielectric layers are typically interconnected through a system of metalized vias. Conventionally, within an array of metal lines, the direction longitudinal, or parallel, to the metal lines is designated the “Y” direction and the direction perpendicular, or lateral, to the metal lines is designated the “X” direction.
In order to provide functionality between devices, such as transistors, capacitors and the like, in the integrated circuit, a plurality of continuity cuts (also referred to as continuity blocks) must be lithographically patterned into the metal lines at specific locations to direct current flow between the dielectric layers and the devices. Problematically however, lithographic misalignment is a significant issue at lower technology node sizes, such as when the repetitive pitch distance between metal lines is no greater than 40 nanometers (nm). Lithographic misalignment is a measure of how well two lithographic layers (or steps) align.
The lithographically disposed continuity cuts must be large enough to make sure that they cut the metal lines they are supposed to without clipping any neighboring lines, taking into account worst case tolerance conditions. However, this becomes increasingly problematic as the metal line pitch on an interconnection system becomes increasingly smaller, for example smaller than 40 nm. The unwanted over-extension of continuity cuts into neighboring lines can, in the worst case condition, completely interrupt electrical continuity in the wrong line.
Additionally, continuity cuts can vary drastically in size within an array of metal lines disposed in a dielectric layer of an integrated circuit. For example, there may be small cuts (e.g., about the width of a single metal line or a single minimum pitch length) required to block continuity, and there may also be large cuts (e.g., several pitch lengths in width) which are used to define a transition region from multiple minimum width metal lines to a much larger width single metal line. Additionally, the largest cuts of all are often used to define an ANA region bordering the metal line array in which no metal lines or active devices can exist. This variability in the size of continuity cuts is very difficult to achieve with prior art lithographic techniques.
Moreover for smaller pitches, for example pitches of 40 nm or less, it becomes increasingly problematic for prior art lithographic processes to cut (or block the formation of) a dummy (or inactive) metal line from between two active metal lines in an array of metal lines. Often times in an interconnection system, not all of the metal lines will be active. Due to conventional lithographic limitations, these dummy lines are typically left disposed in the dielectric layer between active lines. Problematically however, the dummy lines increase the parasitic capacitance between the active lines and, as such, degrade performance.
Accordingly, there is a need for a method of more precisely and easily forming variable continuity cuts in arrays of metal lines of an integrated circuit than that of the prior art. More specifically, there is a need for a method of forming cuts in arrays of metal lines of an integrated circuit that can be utilized to provide such functions as:                forming continuity blocks within a single line,        defining transition regions between multiple lines,        defining relatively large ANA regions bordering the array of lines,        blocking the formation of dummy lines from between active lines, or        other similar functions.        